1. Field of the Invention
The present invention relates to a protection component, specifically, a protection component applicable to the protection of telephone circuits.
2. Discussion of the Related Art
European patent application EP-A-0687051, herein incorporated by reference, describes a protection circuit for interface of telephone lines and specific implementations of this circuit in the form of a monolithic component.
FIG. 1 of the present application reproduces FIG. 4 of this prior patent application and shows a circuit component including two head-to-tail thyristors Th1 and Th2, respectively a cathode-gate thyristor and an anode-gate thyristor connected between a line AB and a reference terminal G. The gates are connected together to a node or terminal B. A common terminal of the thyristors is connected to a node or terminal A, a resistor Rd being inserted between the nodes A and B. The other common terminal of the thyristors is connected to reference terminal G. A Zener diode Z1 connected between terminals B and G triggers, when it avalanches, thyristor Th1, and a Zener diode Z2 connected between terminals A and G triggers, when it avalanches, thyristor Th2. When the current between terminals A and B exceeds a determined threshold, one or the other of thyristors Th1 and Th2 is turned on by its gate.
Thus, in the circuit of FIG. 1, according to the involved biasing, one or the other of thyristors Th1 and Th2 turns on if the current through resistor Rd exceeds a determined threshold or if the voltage on line AB exceeds the avalanche voltage of diode Z1 or Z2.
FIG. 2 of the present application reproduces FIG. 7 of the above-mentioned patent application and shows an embodiment of the circuit of FIG. 1. The indication of the locations of components Th1, Th2, Z1, and Z2 of FIG. 1 has been included in FIG. 2.
However, in the practical implementation of the circuit, the applicant noticed that, although the triggering of thyristor Th1 after the starting of the avalanche of Zener diode Z1 does not raise any specific problem, the triggering sensitivity of thyristor Th2 after the passing of a current through resistor Rd should still be improved. More specifically, this triggering takes too long, having a duration longer than 1 .mu.s. Efforts for optimizing the topology of the component (see FIGS. 8A and 8B of European patent application EP-A-068705) have yielded no results. When an overvoltage with a particularly steep edge (for example, a standardized 0.5/700 .mu.s wave with a 30 A intensity) occurs on line AB, thyristor Th2 turns on only after a certain delay and, during this delay, the protection component lets through the peak intensity of 30 A, which can damage the integrated circuit to be protected.
To solve this problem and improve the reaction speed of the component after the occurrence of a positive overvoltage on line AB, the applicant has provided in European patent application EP-A-0785577 herein incorporated by reference a modification of the structure of the component of FIG. 2 and more specifically of the portion of this component corresponding to thyristor Th2, as is shown in FIG. 3.
FIG. 3 schematically shows an example of monolithic implementation of the circuit of FIG. 1. This component is realized as that of FIG. 2 from an N-type substrate. In the lefthand portion of the component, the same elements as those shown in the left-hand portion of FIG. 2 are designated by the same references.
A difference with respect to the circuit of FIG. 2 is that this assembly of semiconductive layers and regions is formed in a well isolated by P-type isolating walls 11 to isolate the thyristor Th1 and its associated components of thyristor Th2. These walls are formed by conventional and known techniques, including such steps performing a diffusion from the upper and lower surfaces of the substrate. Further, a region P8 of shortcircuit detection is not shown in FIG. 3, but this region can be provided if desired.
The left-hand portion of FIG. 3 includes, at the lower substrate surface, a P-type layer P2 and, at the upper substrate surface, P-type regions P1 and P7 in which are respectively formed N-type regions N1 and N7. At the interface between region P7 and a substrate N, an N-type region N4 is formed.
The lower surface of the wafer is coated with a metallization M2. Region P7 is coated with a metallization M3. Region N7 and a portion of region P1 are coated with a metallization M7. Region N1 is coated with a metallization M1-1 which corresponds to a portion of metallization M1 of FIG. 2.
This structure is an implementation of the assembly of thyristor Th1 and Zener diode Z1 of FIG. 1. Thyristor Th1 includes regions N1-P1-N-P2 and is associated with regions N7 and P7 to form a gate amplification thyristor. Zener diode Z1 is formed by the junction between regions P7 and N4 especially designed to assume this function.
The right-hand portion of FIG. 3 shows a realization of the elements corresponding to the assembly of thyristor Th2 and Zener diode Z2 of FIG. 1. Diode Z2 corresponds to one of the junctions of the thyristor which is a forward break-over thyristor. This structure may be formed in a well isolated by P-type isolating walls 12.
In this right-hand portion, the bottom surface is occupied by an N-type heavily-doped layer N11 formed by diffusion or implantation-diffusion. On the top surface, successively formed are a P-type deep diffusion P12; within region P12, an N-type deep diffusion N13; and, within region N13, separate regions P14 of type P and N15 of type N.
Thyristor Th2, from its anode to its cathode, corresponds to regions and layers P14-N13-P12-N-N11. Region N15 is an anode gate contacting region. Anode region P14 is coated with a metallization M1-2 connected to metallization M1-1. Anode gate contacting region N15 is coated with a metallization M4 corresponding to the metallization of same reference in FIG. 2 and connected to terminal B.
In this structure, when thyristor Th2 is forward biased, the junction most likely to avalanche is junction N13-P12. This junction must thus be optimized to have a desired avalanche threshold, preferably close to that of junction P7-N4. Because the regions P12 and M13 are formed by successive diffusions, it is possible to optimize the doping levels and the diffusion profiles so that this junction has the desired features.
Also, if thyristor Th2 is considered as formed of an assembly of a PNP transistor P14-N13-P12 and of an NPN transistor N13-P12-N-N11, the gains of these transistors can be optimized to increase the sensitivity of thyristor Th2.
The creation of such a component does not require any additional steps of manufacturing with respect to those necessary to make the component of FIG. 2 (noting that, although no isolating wall has been illustrated in the partial view of FIG. 2, in practice isolating walls will exist in the general structure to which the component of FIG. 2 belongs). More specifically, region P12 can be made at the same time as the upper portion of isolating walls 11 and 12, region N13 can be made at the same time as region N4, region P14 at the same time as regions PI and P7, and region N15 at the same time as regions N1, N7, and N11. However, although resulting from the same diffusion steps, that is, with a same duration and a same anneal temperature, these diffusions can have distinct doping levels. For instance, the doping level of region P12 will be much lower than that of the isolating walls.
As an example of numeric values, the following approximate values of dopant concentration Cs (in at./cm.sup.3) and of junction depth xj (in .mu.m) can be chosen for various regions:
______________________________________ Cs xj ______________________________________ layer P14 about 10.sup.18 20 layer N15 about 10.sup.20 10 layer N13 about 10.sup.17 40 layer P12 about 10.sup.16 90 layer N11 about 10.sup.20 10 ______________________________________
With the component of FIG. 3, thyristor Th2 starts conducting extremely rapidly after an overvoltage (less than 1 .mu.s after the beginning of the overvoltage). Thus, the component of FIG. 3 satisfactorily solves most of the problems raised.
However, in the implementation of the component of FIG. 3, the applicant has noticed that in some configurations of ring signals, the component triggers undesiredly. The present invention aims at avoiding this drawback.